Implement variable-width shifts
This commit is contained in:
parent
e44b63dd15
commit
b5e3cb7dff
|
@ -723,7 +723,7 @@ addByte:
|
|||
; Calculate carries in r3
|
||||
and r3, r0
|
||||
or r2, r3 ; Accumulate carry into carryout
|
||||
shl r3
|
||||
shl r3, 1
|
||||
; Calculate sums in r0
|
||||
xor r0, r1
|
||||
; Copy carries into second addend
|
||||
|
@ -735,13 +735,8 @@ addByte:
|
|||
brneq r1, r3, addByteLoop
|
||||
|
||||
; Shift carryout, as we want carry from highest place = 1
|
||||
shr r2
|
||||
shr r2
|
||||
shr r2
|
||||
shr r2
|
||||
shr r2
|
||||
shr r2
|
||||
shr r2
|
||||
shr r2, 4
|
||||
shr r2, 3
|
||||
|
||||
; Move carryout to r1
|
||||
; (We know r1 is already 0 since it's the loop condition)
|
||||
|
@ -973,10 +968,7 @@ writehexByte:
|
|||
or r2, r0
|
||||
|
||||
; High nybble
|
||||
shr r0
|
||||
shr r0
|
||||
shr r0
|
||||
shr r0
|
||||
shr r0, 4
|
||||
cleq r0, r0, nybble2hex
|
||||
store ffff, r0
|
||||
|
||||
|
|
|
@ -3,7 +3,7 @@ from collections import namedtuple
|
|||
import enum
|
||||
|
||||
class rfield(enum.Enum):
|
||||
none, reg, imm_flag = range(3)
|
||||
none, reg, imm_flag, shift = range(4)
|
||||
|
||||
Opcode = namedtuple('Opcode', ('mnemonic', 'rx', 'ry', 'addr'))
|
||||
|
||||
|
@ -11,10 +11,10 @@ opcodes = [
|
|||
Opcode('halt', rx=rfield.none, ry=rfield.none, addr=False),
|
||||
Opcode('ret', rx=rfield.none, ry=rfield.none, addr=False),
|
||||
|
||||
Opcode('shl', rx=rfield.reg, ry=rfield.none, addr=False),
|
||||
Opcode('shr', rx=rfield.reg, ry=rfield.none, addr=False),
|
||||
Opcode('rol', rx=rfield.reg, ry=rfield.none, addr=False),
|
||||
Opcode('ror', rx=rfield.reg, ry=rfield.none, addr=False),
|
||||
Opcode('shl', rx=rfield.reg, ry=rfield.shift, addr=False),
|
||||
Opcode('shr', rx=rfield.reg, ry=rfield.shift, addr=False),
|
||||
Opcode('rol', rx=rfield.reg, ry=rfield.shift, addr=False),
|
||||
Opcode('ror', rx=rfield.reg, ry=rfield.shift, addr=False),
|
||||
|
||||
Opcode('nand', rx=rfield.reg, ry=rfield.reg, addr=False),
|
||||
Opcode('and', rx=rfield.reg, ry=rfield.reg, addr=False),
|
||||
|
@ -89,6 +89,9 @@ def disasm(binary, origin = 0):
|
|||
fields.append(f'r{contents.rx}')
|
||||
if opcodes[contents.opcode].ry == rfield.reg:
|
||||
fields.append(f'r{contents.ry}')
|
||||
elif opcodes[contents.opcode].ry == rfield.shift:
|
||||
shift = contents.ry if contents.ry != 0 else 4
|
||||
fields.append(f'{shift}')
|
||||
if contents.immediate is not None:
|
||||
fields.append(f'#{contents.immediate:02x}')
|
||||
elif opcodes[contents.opcode].addr:
|
||||
|
|
Loading…
Reference in New Issue