I hereby relicense all my work on Sortix under the ISC license as below. All Sortix contributions by other people are already under this license, are not substantial enough to be copyrightable, or have been removed. All imported code from other projects is compatible with this license. All GPL licensed code from other projects had previously been removed. Copyright 2011-2016 Jonas 'Sortie' Termansen and contributors. Permission to use, copy, modify, and distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
717 lines
18 KiB
C++
717 lines
18 KiB
C++
/*
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* Copyright (c) 2013, 2014, 2015, 2016 Jonas 'Sortie' Termansen.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* disk/ahci/port.cpp
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* Driver for the Advanced Host Controller Interface.
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*/
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#include <assert.h>
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#include <errno.h>
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#include <endian.h>
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#include <stdarg.h>
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#include <stdint.h>
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#include <string.h>
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#include <time.h>
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#include <timespec.h>
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#include <sortix/clock.h>
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#include <sortix/mman.h>
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#include <sortix/kernel/addralloc.h>
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#include <sortix/kernel/clock.h>
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#include <sortix/kernel/ioctx.h>
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#include <sortix/kernel/kthread.h>
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#include <sortix/kernel/log.h>
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#include <sortix/kernel/memorymanagement.h>
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#include <sortix/kernel/signal.h>
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#include <sortix/kernel/time.h>
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#include "ahci.h"
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#include "hba.h"
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#include "port.h"
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#include "registers.h"
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namespace Sortix {
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namespace AHCI {
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// TODO: Is this needed?
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static inline void ahci_port_flush(volatile struct port_regs* port_regs)
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{
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(void) port_regs->pxcmd;
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}
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static inline void delay(int usecs)
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{
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struct timespec delay = timespec_make(usecs / 1000000, usecs * 1000);
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Clock* clock = Time::GetClock(CLOCK_BOOT);
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clock->SleepDelay(delay);
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}
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static void copy_ata_string(char* dest, const char* src, size_t length)
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{
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for ( size_t i = 0; i < length; i += 2 )
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{
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dest[i + 0] = src[i + 1];
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dest[i + 1] = src[i + 0];
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}
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length = strnlen(dest, length);
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while ( 0 < length && dest[length - 1] == ' ' )
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length--;
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dest[length] = '\0';
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}
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Port::Port(HBA* hba, uint32_t port_index)
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{
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port_lock = KTHREAD_MUTEX_INITIALIZER;
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memset(&control_alloc, 0, sizeof(control_alloc));
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memset(&dma_alloc, 0, sizeof(dma_alloc));
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this->hba = hba;
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regs = &hba->regs->ports[port_index];
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control_physical_frame = 0;
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dma_physical_frame = 0;
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this->port_index = port_index;
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is_control_page_mapped = false;
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is_dma_page_mapped = false;
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interrupt_signaled = false;
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transfer_in_progress = false;
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}
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Port::~Port()
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{
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if ( transfer_in_progress )
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FinishTransferDMA();
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if ( is_control_page_mapped )
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Memory::Unmap(control_alloc.from);
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FreeKernelAddress(&control_alloc);
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if ( is_dma_page_mapped )
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Memory::Unmap(dma_alloc.from);
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FreeKernelAddress(&dma_alloc);
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if ( control_physical_frame )
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Page::Put(control_physical_frame, PAGE_USAGE_DRIVER);
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if ( dma_physical_frame )
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Page::Put(dma_physical_frame, PAGE_USAGE_DRIVER);
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}
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void Port::LogF(const char* format, ...)
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{
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// TODO: Print this line in an atomic manner.
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Log::PrintF("ahci: pci 0x%X: port %u: ", hba->devaddr, port_index);
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va_list ap;
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va_start(ap, format);
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Log::PrintFV(format, ap);
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va_end(ap);
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Log::PrintF("\n");
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}
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bool Port::Initialize()
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{
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// TODO: Potentially move the wait-for-device-to-be-idle code here from hba.
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// Clear interrupt status.
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regs->pxis = regs->pxis;
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// Clear error bits.
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regs->pxserr = regs->pxserr;
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if ( !(control_physical_frame = Page::Get(PAGE_USAGE_DRIVER)) )
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{
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LogF("error: control page allocation failure");
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return false;
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}
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if ( !(dma_physical_frame = Page::Get(PAGE_USAGE_DRIVER)) )
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{
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LogF("error: dma page allocation failure");
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return false;
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}
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if ( !AllocateKernelAddress(&control_alloc, Page::Size()) )
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{
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LogF("error: control page virtual address allocation failure");
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return false;
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}
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if ( !AllocateKernelAddress(&dma_alloc, Page::Size()) )
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{
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LogF("error: dma page virtual address allocation failure");
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return false;
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}
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int prot = PROT_KREAD | PROT_KWRITE;
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is_control_page_mapped =
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Memory::Map(control_physical_frame, control_alloc.from, prot);
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if ( !is_control_page_mapped )
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{
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LogF("error: control page virtual address allocation failure");
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return false;
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}
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Memory::Flush();
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is_dma_page_mapped = Memory::Map(dma_physical_frame, dma_alloc.from, prot);
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if ( !is_dma_page_mapped )
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{
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LogF("dma page virtual address allocation failure");
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return false;
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}
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Memory::Flush();
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return true;
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}
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bool Port::FinishInitialize()
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{
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// Disable power management transitions for now (IPM = 3 = transitions to
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// partial/slumber disabled).
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regs->pxsctl = regs->pxsctl | 0x300 /* TODO: Magic constant? */;
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// Power on and spin up the device if necessary.
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if ( regs->pxcmd & PXCMD_CPD )
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regs->pxcmd = regs->pxcmd | PXCMD_POD;
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if ( hba->regs->cap & CAP_SSS )
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regs->pxcmd = regs->pxcmd | PXCMD_SUD;
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// Activate the port.
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regs->pxcmd = (regs->pxcmd & ~PXCMD_ICC(16)) | (1 << 28);
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if ( !Reset() )
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{
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// TODO: Is this safe?
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return false;
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}
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// Clear interrupt status.
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regs->pxis = regs->pxis;
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// Clear error bits.
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regs->pxserr = regs->pxserr;
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uintptr_t virt = control_alloc.from;
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uintptr_t phys = control_physical_frame;
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memset((void*) virt, 0, Page::Size());
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size_t offset = 0;
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clist = (volatile struct command_header*) (virt + offset);
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uint64_t pxclb_addr = phys + offset;
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regs->pxclb = pxclb_addr >> 0;
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regs->pxclbu = pxclb_addr >> 32;
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offset += sizeof(struct command_header) * AHCI_COMMAND_HEADER_COUNT;
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fis = (volatile struct fis*) (virt + offset);
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uint64_t pxf_addr = phys + offset;
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regs->pxfb = pxf_addr >> 0;
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regs->pxfbu = pxf_addr >> 32;
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offset += sizeof(struct fis);
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ctbl = (volatile struct command_table*) (virt + offset);
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uint64_t ctba_addr = phys + offset;
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clist[0].ctba = ctba_addr >> 0;
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clist[0].ctbau = ctba_addr >> 32;
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offset += sizeof(struct command_table);
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prdt = (volatile struct prd*) (virt + offset);
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offset += sizeof(struct prd);
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// TODO: There can be more of these, fill until end of page!
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// Enable FIS receive.
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regs->pxcmd = regs->pxcmd | PXCMD_FRE;
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ahci_port_flush(regs);
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assert(offset <= Page::Size());
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uint32_t ssts = regs->pxssts;
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uint32_t pxtfd = regs->pxtfd;
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if ( (ssts & 0xF) != 0x3 )
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return false;
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if ( pxtfd & ATA_STATUS_BSY )
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return false;
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if ( pxtfd & ATA_STATUS_DRQ )
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return false;
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// TODO: ATAPI.
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if ( regs->pxsig == 0xEB140101 )
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return false;
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// Start DMA engine.
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if ( regs->pxcmd & PXCMD_CR )
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{
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if ( !WaitClear(®s->pxcmd, PXCMD_CR, false, 500) )
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{
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LogF("error: timeout waiting for PXCMD_CR to clear");
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return false;
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}
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}
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regs->pxcmd = regs->pxcmd | PXCMD_ST;
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ahci_port_flush(regs);
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// Set which interrupts we want to know about.
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regs->pxie = PORT_INTR_ERROR | PXIE_DHRE | PXIE_PSE |
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PXIE_DSE | PXIE_SDBE | PXIE_DPE;
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ahci_port_flush(regs);
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CommandDMA(ATA_CMD_IDENTIFY, 512, false);
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if ( !AwaitInterrupt(500 /*ms*/) )
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{
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LogF("error: IDENTIFY timed out");
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return false;
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}
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transfer_in_progress = false;
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memcpy(identify_data, (void*) dma_alloc.from, sizeof(identify_data));
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little_uint16_t* words = (little_uint16_t*) dma_alloc.from;
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if ( words[0] & (1 << 15) )
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return errno = EINVAL, false; // Skipping non-ATA device.
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if ( !(words[49] & (1 << 9)) )
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return errno = EINVAL, false; // Skipping non-LBA device.
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this->is_lba48 = words[83] & (1 << 10);
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copy_ata_string(serial, (const char*) &words[10], sizeof(serial) - 1);
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copy_ata_string(revision, (const char*) &words[23], sizeof(revision) - 1);
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copy_ata_string(model, (const char*) &words[27], sizeof(model) - 1);
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uint64_t block_count;
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if ( is_lba48 )
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{
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block_count = (uint64_t) words[100] << 0 |
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(uint64_t) words[101] << 16 |
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(uint64_t) words[102] << 32 |
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(uint64_t) words[103] << 48;
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}
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else
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{
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block_count = (uint64_t) words[60] << 0 |
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(uint64_t) words[61] << 16;
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}
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uint64_t block_size = 512;
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if( (words[106] & (1 << 14)) &&
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!(words[106] & (1 << 15)) &&
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(words[106] & (1 << 12)) )
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{
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block_size = 2 * ((uint64_t) words[117] << 0 |
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(uint64_t) words[118] << 16);
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}
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// TODO: Verify the block size is a power of two.
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cylinder_count = words[1];
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head_count = words[3];
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sector_count = words[6];
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// TODO: Verify that DMA is properly supported.
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// See kiwi/source/drivers/bus/ata/device.c line 344.
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if ( __builtin_mul_overflow(block_count, block_size, &this->device_size) )
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{
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LogF("error: device size overflows off_t");
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return errno = EOVERFLOW, false;
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}
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this->block_count = (blkcnt_t) block_count;
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this->block_size = (blkcnt_t) block_size;
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return true;
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}
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bool Port::Reset()
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{
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if ( regs->pxcmd & (PXCMD_ST | PXCMD_CR) )
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{
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regs->pxcmd = regs->pxcmd & ~PXCMD_ST;
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if ( !WaitClear(®s->pxcmd, PXCMD_CR, false, 500) )
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{
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LogF("error: timeout waiting for PXCMD_CR to clear");
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return false;
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}
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}
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if ( regs->pxcmd & (PXCMD_FRE | PXCMD_FR) )
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{
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regs->pxcmd = regs->pxcmd & ~PXCMD_FRE;
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if ( !WaitClear(®s->pxcmd, PXCMD_FR, false, 500) )
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{
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LogF("error: timeout waiting for PXCMD_FR to clear");
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return false;
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}
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}
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#if 0
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// Reset the device
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regs->pxsctl = (regs->pxsctl & ~0xF) | 1;
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ahci_port_flush(regs);
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delay(1500);
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regs->pxsctl = (regs->pxsctl & ~0xF);
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ahci_port_flush(regs);
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#endif
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// Wait for the device to be detected.
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if ( !WaitSet(®s->pxssts, 0x1, false, 600) )
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return false;
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// Clear error.
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regs->pxserr = regs->pxserr;
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ahci_port_flush(regs);
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// Wait for communication to be established with device
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if ( regs->pxssts & 0x1 )
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{
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if ( !WaitSet(®s->pxssts, 0x3, false, 600) )
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return false;
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regs->pxserr = regs->pxserr;
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ahci_port_flush(regs);
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}
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// Wait for the device to come back up.
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if ( (regs->pxtfd & 0xFF) == 0xFF )
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{
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delay(500 * 1000);
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if ( (regs->pxtfd & 0xFF) == 0xFF )
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{
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LogF("error: device did not come back up after reset");
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return errno = EINVAL, false;
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}
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}
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#if 0
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if ( !WaitClear(®s->pxtfd, ATA_STATUS_BSY, false, 1000) )
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{
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LogF("error: device did not unbusy");
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return false;
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}
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#endif
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return true;
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}
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void Port::Seek(blkcnt_t block_index, size_t count)
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{
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uintmax_t lba = (uintmax_t) block_index;
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if ( is_lba48 )
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{
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memset((void *)&ctbl->cfis, 0, sizeof(ctbl->cfis));
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ctbl->cfis.count_0_7 = (count >> 0) & 0xff;
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ctbl->cfis.count_8_15 = (count >> 8) & 0xff;
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ctbl->cfis.lba_0_7 = (lba >> 0) & 0xff;
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ctbl->cfis.lba_8_15 = (lba >> 8) & 0xff;
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ctbl->cfis.lba_16_23 = (lba >> 16) & 0xff;
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ctbl->cfis.lba_24_31 = (lba >> 24) & 0xff;
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ctbl->cfis.lba_32_39 = (lba >> 32) & 0xff;
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ctbl->cfis.lba_40_47 = (lba >> 40) & 0xff;
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ctbl->cfis.device = 0x40;
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}
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else
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{
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ctbl->cfis.count_0_7 = (count >> 0) & 0xff;
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ctbl->cfis.lba_0_7 = (lba >> 0) & 0xff;
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ctbl->cfis.lba_8_15 = (lba >> 8) & 0xff;
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ctbl->cfis.lba_16_23 = (lba >> 16) & 0xff;
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ctbl->cfis.device = 0x40 | ((lba >> 24) & 0xf);
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}
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}
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void Port::CommandDMA(uint8_t cmd, size_t size, bool write)
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{
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if ( 0 < size )
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{
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assert(size <= Page::Size());
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assert((size & 1) == 0); /* sizes & addresses must be 2-byte aligned */
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}
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// Set up the command header.
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uint16_t fis_length = 5 /* dwords */;
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uint16_t prdtl = size ? 1 : 0;
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uint16_t clist_0_dw0l = fis_length;
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if ( write )
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clist_0_dw0l |= COMMAND_HEADER_DW0_WRITE;
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clist[0].dw0l = clist_0_dw0l;
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clist[0].prdtl = prdtl;
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clist[0].prdbc = 0;
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// Set up the physical region descriptor.
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if ( prdtl )
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{
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uint32_t prdt_0_dbc = size - 1;
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uint32_t prdt_0_dw3 = prdt_0_dbc;
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prdt[0].dba = (uint64_t) dma_physical_frame >> 0 & 0xFFFFFFFF;
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prdt[0].dbau = (uint64_t) dma_physical_frame >> 32 & 0xFFFFFFFF;
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prdt[0].reserved1 = 0;
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prdt[0].dw3 = prdt_0_dw3;
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}
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// Set up the command table.
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ctbl->cfis.type = 0x27;
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ctbl->cfis.pm_port = 0;
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ctbl->cfis.c_bit = 1;
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ctbl->cfis.command = cmd;
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// Anticipate we will be delivered an IRQ.
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PrepareAwaitInterrupt();
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transfer_in_progress = true;
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transfer_size = size;
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transfer_is_write = write;
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// Execute the command.
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regs->pxci = 1;
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ahci_port_flush(regs);
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}
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bool Port::FinishTransferDMA()
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{
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assert(transfer_in_progress);
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// Wait for an interrupt to arrive.
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if ( !AwaitInterrupt(10000 /*ms*/) )
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{
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const char* op = transfer_is_write ? "write" : "read";
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LogF("error: %s timed out", op);
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transfer_in_progress = false;
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return errno = EIO, false;
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}
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while ( transfer_is_write && regs->pxtfd & ATA_STATUS_BSY )
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kthread_yield();
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|
|
transfer_in_progress = false;
|
|
return true;
|
|
}
|
|
|
|
off_t Port::GetSize()
|
|
{
|
|
return device_size;
|
|
}
|
|
|
|
blkcnt_t Port::GetBlockCount()
|
|
{
|
|
return block_count;
|
|
}
|
|
|
|
blksize_t Port::GetBlockSize()
|
|
{
|
|
return block_size;
|
|
}
|
|
|
|
uint16_t Port::GetCylinderCount()
|
|
{
|
|
return cylinder_count;
|
|
}
|
|
|
|
uint16_t Port::GetHeadCount()
|
|
{
|
|
return head_count;
|
|
}
|
|
|
|
uint16_t Port::GetSectorCount()
|
|
{
|
|
return sector_count;
|
|
}
|
|
|
|
const char* Port::GetDriver()
|
|
{
|
|
return "ahci";
|
|
}
|
|
|
|
const char* Port::GetModel()
|
|
{
|
|
return model;
|
|
}
|
|
|
|
const char* Port::GetSerial()
|
|
{
|
|
return serial;
|
|
}
|
|
|
|
const char* Port::GetRevision()
|
|
{
|
|
return revision;
|
|
}
|
|
|
|
const unsigned char* Port::GetATAIdentify(size_t* size_ptr)
|
|
{
|
|
return *size_ptr = sizeof(identify_data), identify_data;
|
|
}
|
|
|
|
int Port::sync(ioctx_t* ctx)
|
|
{
|
|
(void) ctx;
|
|
ScopedLock lock(&port_lock);
|
|
if ( transfer_in_progress && !FinishTransferDMA() )
|
|
return -1;
|
|
PrepareAwaitInterrupt();
|
|
uint8_t cmd = is_lba48 ? ATA_CMD_FLUSH_CACHE_EXT : ATA_CMD_FLUSH_CACHE;
|
|
CommandDMA(cmd, 0, false);
|
|
// TODO: This might take longer than 30 seconds according to the spec. But
|
|
// how long? Let's say twice that?
|
|
if ( !AwaitInterrupt(2 * 30000 /*ms*/) )
|
|
{
|
|
LogF("error: cache flush timed out");
|
|
transfer_in_progress = false;
|
|
return errno = EIO, -1;
|
|
}
|
|
transfer_in_progress = false;
|
|
if ( regs->pxtfd & (ATA_STATUS_ERR | ATA_STATUS_DF) )
|
|
{
|
|
LogF("error: IO error");
|
|
return errno = EIO, -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
ssize_t Port::pread(ioctx_t* ctx, unsigned char* buf, size_t count, off_t off)
|
|
{
|
|
ScopedLock lock(&port_lock);
|
|
ssize_t result = 0;
|
|
while ( count )
|
|
{
|
|
if ( device_size <= off )
|
|
break;
|
|
if ( (uintmax_t) device_size - off < (uintmax_t) count )
|
|
count = (size_t) device_size - off;
|
|
uintmax_t block_index = (uintmax_t) off / (uintmax_t) block_size;
|
|
uintmax_t block_offset = (uintmax_t) off % (uintmax_t) block_size;
|
|
uintmax_t amount = block_offset + count;
|
|
if ( Page::Size() < amount )
|
|
amount = Page::Size();
|
|
size_t num_blocks = (amount + block_size - 1) / block_size;
|
|
uintmax_t full_amount = num_blocks * block_size;
|
|
// If an asynchronous operation is in progress, let it finish.
|
|
if ( transfer_in_progress && !FinishTransferDMA() )
|
|
return result ? result : -1;
|
|
unsigned char* dma_data = (unsigned char*) dma_alloc.from;
|
|
unsigned char* data = dma_data + block_offset;
|
|
size_t data_size = amount - block_offset;
|
|
Seek(block_index, num_blocks);
|
|
uint8_t cmd = is_lba48 ? ATA_CMD_READ_DMA_EXT : ATA_CMD_READ_DMA;
|
|
CommandDMA(cmd, (size_t) full_amount, false);
|
|
if ( !FinishTransferDMA() )
|
|
return result ? result : -1;
|
|
if ( !ctx->copy_to_dest(buf, data, data_size) )
|
|
return result ? result : -1;
|
|
buf += data_size;
|
|
count -= data_size;
|
|
result += data_size;
|
|
off += data_size;
|
|
}
|
|
return result;
|
|
}
|
|
|
|
ssize_t Port::pwrite(ioctx_t* ctx, const unsigned char* buf, size_t count, off_t off)
|
|
{
|
|
ScopedLock lock(&port_lock);
|
|
ssize_t result = 0;
|
|
while ( count )
|
|
{
|
|
if ( device_size <= off )
|
|
break;
|
|
if ( (uintmax_t) device_size - off < (uintmax_t) count )
|
|
count = (size_t) device_size - off;
|
|
uintmax_t block_index = (uintmax_t) off / (uintmax_t) block_size;
|
|
uintmax_t block_offset = (uintmax_t) off % (uintmax_t) block_size;
|
|
uintmax_t amount = block_offset + count;
|
|
if ( Page::Size() < amount )
|
|
amount = Page::Size();
|
|
size_t num_blocks = (amount + block_size - 1) / block_size;
|
|
uintmax_t full_amount = num_blocks * block_size;
|
|
// If an asynchronous operation is in progress, let it finish.
|
|
if ( transfer_in_progress && !FinishTransferDMA() )
|
|
return result ? result : -1;
|
|
unsigned char* dma_data = (unsigned char*) dma_alloc.from;
|
|
unsigned char* data = dma_data + block_offset;
|
|
size_t data_size = amount - block_offset;
|
|
if ( block_offset || amount < full_amount )
|
|
{
|
|
Seek(block_index, num_blocks);
|
|
uint8_t cmd = is_lba48 ? ATA_CMD_READ_DMA_EXT : ATA_CMD_READ_DMA;
|
|
CommandDMA(cmd, (size_t) full_amount, false);
|
|
if ( !FinishTransferDMA() )
|
|
return result ? result : -1;
|
|
}
|
|
if ( !ctx->copy_from_src(data, buf, data_size) )
|
|
return result ? result : -1;
|
|
Seek(block_index, num_blocks);
|
|
uint8_t cmd = is_lba48 ? ATA_CMD_WRITE_DMA_EXT : ATA_CMD_WRITE_DMA;
|
|
CommandDMA(cmd, (size_t) full_amount, true);
|
|
// Let the transfer finish asynchronously so the caller can prepare the
|
|
// next write operation to keep the write pipeline busy.
|
|
buf += data_size;
|
|
count -= data_size;
|
|
result += data_size;
|
|
off += data_size;
|
|
}
|
|
return result;
|
|
}
|
|
|
|
void Port::PrepareAwaitInterrupt()
|
|
{
|
|
interrupt_signaled = false;
|
|
}
|
|
|
|
bool Port::AwaitInterrupt(unsigned int msecs)
|
|
{
|
|
struct timespec timeout = timespec_make(msecs / 1000, (msecs % 1000) * 1000000L);
|
|
Clock* clock = Time::GetClock(CLOCK_BOOT);
|
|
struct timespec begun;
|
|
clock->Get(&begun, NULL);
|
|
while ( true )
|
|
{
|
|
struct timespec now;
|
|
clock->Get(&now, NULL);
|
|
if ( interrupt_signaled )
|
|
return true;
|
|
struct timespec elapsed = timespec_sub(now, begun);
|
|
if ( timespec_le(timeout, elapsed) )
|
|
return errno = ETIMEDOUT, false;
|
|
// TODO: Can't safely back out here unless the pending operation is
|
|
// is properly cancelled.
|
|
//if ( Signal::IsPending() )
|
|
// return errno = EINTR, false;
|
|
kthread_yield();
|
|
}
|
|
}
|
|
|
|
void Port::OnInterrupt()
|
|
{
|
|
// Check whether any interrupt are pending.
|
|
uint32_t is = regs->pxis;
|
|
if ( !is )
|
|
return;
|
|
|
|
// Clear the pending interrupts.
|
|
regs->pxis = is;
|
|
|
|
// Handle error interrupts.
|
|
if ( is & PORT_INTR_ERROR )
|
|
{
|
|
regs->pxserr = regs->pxserr;
|
|
// TODO: How exactly should this be handled?
|
|
}
|
|
|
|
if ( !interrupt_signaled )
|
|
{
|
|
interrupt_signaled = true;
|
|
// TODO: Priority schedule the blocking thread now.
|
|
}
|
|
}
|
|
|
|
} // namespace AHCI
|
|
} // namespace Sortix
|