Enable the NX bit on x86_64 and set if not PROT_EXEC and enable the write protection mode (CR0.WP) that disables the default behavior where the kernel is able to write to read-only memory. Fix kernel broken assumptions it can access read-only memory and take care to never set PROT_KWRITE on user-space pages unless PROT_WRITE is also set, otherwise user-space will be able to write to read-only memory. This achieves X^W in the whole system except for the core kernel itself as it is currently don't know the purpose of pages when identity mapping the first 4 MiB.
115 lines
3 KiB
C++
115 lines
3 KiB
C++
/*******************************************************************************
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Copyright(C) Jonas 'Sortie' Termansen 2011, 2012, 2014, 2015.
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This file is part of Sortix.
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Sortix is free software: you can redistribute it and/or modify it under the
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terms of the GNU General Public License as published by the Free Software
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Foundation, either version 3 of the License, or (at your option) any later
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version.
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Sortix is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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details.
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You should have received a copy of the GNU General Public License along with
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Sortix. If not, see <http://www.gnu.org/licenses/>.
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x86-family/memorymanagement.h
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Handles memory for the x86 family of architectures.
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*******************************************************************************/
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#ifndef SORTIX_X86_FAMILY_MEMORYMANAGEMENT_H
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#define SORTIX_X86_FAMILY_MEMORYMANAGEMENT_H
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namespace Sortix {
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struct PML
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{
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addr_t entry[4096 / sizeof(addr_t)];
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};
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} // namespace Sortix
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namespace Sortix {
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namespace Memory {
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const addr_t PML_PRESENT = 1 << 0;
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const addr_t PML_WRITABLE = 1 << 1;
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const addr_t PML_USERSPACE = 1 << 2;
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const addr_t PML_WRTHROUGH = 1 << 3;
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const addr_t PML_NOCACHE = 1 << 4;
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const addr_t PML_PAT = 1 << 7;
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const addr_t PML_AVAILABLE1 = 1 << 9;
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const addr_t PML_AVAILABLE2 = 1 << 10;
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const addr_t PML_AVAILABLE3 = 1 << 11;
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const addr_t PML_FORK = PML_AVAILABLE1;
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#ifdef __x86_64__
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const addr_t PML_NX = 1UL << 63;
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#else
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const addr_t PML_NX = 0;
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#endif
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const addr_t PML_FLAGS = 0xFFFUL | PML_NX; // Bits used for the flags.
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const addr_t PML_ADDRESS = ~PML_FLAGS; // Bits used for the address.
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const addr_t PAT_UC = 0x00; // Uncacheable
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const addr_t PAT_WC = 0x01; // Write-Combine
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const addr_t PAT_WT = 0x04; // Writethrough
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const addr_t PAT_WP = 0x05; // Write-Protect
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const addr_t PAT_WB = 0x06; // Writeback
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const addr_t PAT_UCM = 0x07; // Uncacheable, overruled by MTRR.
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const addr_t PAT_NUM = 0x08;
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// Desired PAT-Register PA-Field Indexing (different from BIOS defaults)
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const addr_t PA[PAT_NUM] =
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{
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PAT_WB,
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PAT_WT,
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PAT_UCM,
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PAT_UC,
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PAT_WC,
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PAT_WP,
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0,
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0,
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};
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// Inverse function of the above.
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const addr_t PAINV[PAT_NUM] =
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{
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3, // UC
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4, // WC
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7, // No such
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8, // No such
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1, // WT
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5, // WP,
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0, // WB
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2, // UCM
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};
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static inline addr_t EncodePATAsPMLFlag(addr_t pat)
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{
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pat = PAINV[pat];
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addr_t result = 0;
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if ( pat & 0x1 ) { result |= PML_WRTHROUGH; }
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if ( pat & 0x2 ) { result |= PML_NOCACHE; }
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if ( pat & 0x4 ) { result |= PML_PAT; }
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return result;
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}
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bool MapPAT(addr_t physical, addr_t mapto, int prot, addr_t mtype);
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addr_t ProtectionToPMLFlags(int prot);
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int PMLFlagsToProtection(addr_t flags);
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} // namespace Memory
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} // namespace Sortix
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#if defined(__i386__)
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#include "../x86/memorymanagement.h"
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#elif defined(__x86_64__)
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#include "../x64/memorymanagement.h"
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#endif
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#endif
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