I hereby relicense all my work on Sortix under the ISC license as below. All Sortix contributions by other people are already under this license, are not substantial enough to be copyrightable, or have been removed. All imported code from other projects is compatible with this license. All GPL licensed code from other projects had previously been removed. Copyright 2011-2016 Jonas 'Sortie' Termansen and contributors. Permission to use, copy, modify, and distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
534 lines
13 KiB
ArmAsm
534 lines
13 KiB
ArmAsm
/*
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* Copyright (c) 2011, 2012, 2013, 2014, 2015 Jonas 'Sortie' Termansen.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* x86/interrupt.S
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* Transfers control to interrupt handlers when interrupts happen.
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*/
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.section .text
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.global isr0
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.type isr0, @function
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isr0:
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pushl $0 # err_code
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pushl $0 # int_no
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jmp interrupt_handler_prepare
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.global isr1
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.type isr1, @function
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isr1:
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pushl $0 # err_code
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pushl $1 # int_no
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jmp interrupt_handler_prepare
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.global isr2
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.type isr2, @function
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isr2:
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pushl $0 # err_code
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pushl $2 # int_no
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jmp interrupt_handler_prepare
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.global isr3
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.type isr3, @function
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isr3:
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pushl $0 # err_code
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pushl $3 # int_no
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jmp interrupt_handler_prepare
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.global isr4
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.type isr4, @function
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isr4:
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pushl $0 # err_code
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pushl $4 # int_no
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jmp interrupt_handler_prepare
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.global isr5
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.type isr5, @function
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isr5:
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pushl $0 # err_code
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pushl $5 # int_no
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jmp interrupt_handler_prepare
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.global isr6
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.type isr6, @function
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isr6:
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pushl $0 # err_code
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pushl $6 # int_no
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jmp interrupt_handler_prepare
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.global isr7
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.type isr7, @function
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isr7:
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pushl $0 # err_code
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pushl $7 # int_no
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jmp interrupt_handler_prepare
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.global isr8
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.type isr8, @function
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isr8:
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# pushl $0 # err_code pushed by CPU
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pushl $8 # int_no
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jmp interrupt_handler_prepare
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.global isr9
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.type isr9, @function
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isr9:
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pushl $0 # err_code
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pushl $9 # int_no
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jmp interrupt_handler_prepare
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.global isr10
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.type isr10, @function
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isr10:
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# pushl $0 # err_code pushed by CPU
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pushl $10 # int_no
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jmp interrupt_handler_prepare
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.global isr11
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.type isr11, @function
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isr11:
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# pushl $0 # err_code pushed by CPU
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pushl $11 # int_no
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jmp interrupt_handler_prepare
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.global isr12
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.type isr12, @function
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isr12:
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# pushl $0 # err_code pushed by CPU
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pushl $12 # int_no
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jmp interrupt_handler_prepare
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.global isr13
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.type isr13, @function
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isr13:
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# pushl $0 # err_code pushed by CPU
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pushl $13 # int_no
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jmp interrupt_handler_prepare
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.global isr14
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.type isr14, @function
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isr14:
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# pushl $0 # err_code pushed by CPU
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pushl $14 # int_no
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jmp interrupt_handler_prepare
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.global isr15
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.type isr15, @function
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isr15:
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pushl $0 # err_code
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pushl $15 # int_no
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jmp interrupt_handler_prepare
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.global isr16
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.type isr16, @function
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isr16:
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pushl $0 # err_code
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pushl $16 # int_no
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jmp interrupt_handler_prepare
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.global isr17
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.type isr17, @function
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isr17:
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# pushl $0 # err_code pushed by CPU
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pushl $17 # int_no
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jmp interrupt_handler_prepare
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.global isr18
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.type isr18, @function
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isr18:
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pushl $0 # err_code
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pushl $18 # int_no
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jmp interrupt_handler_prepare
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.global isr19
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.type isr19, @function
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isr19:
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pushl $0 # err_code
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pushl $19 # int_no
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jmp interrupt_handler_prepare
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.global isr20
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.type isr20, @function
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isr20:
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pushl $0 # err_code
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pushl $20 # int_no
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jmp interrupt_handler_prepare
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.global isr21
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.type isr21, @function
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isr21:
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pushl $0 # err_code
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pushl $21 # int_no
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jmp interrupt_handler_prepare
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.global isr22
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.type isr22, @function
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isr22:
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pushl $0 # err_code
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pushl $22 # int_no
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jmp interrupt_handler_prepare
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.global isr23
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.type isr23, @function
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isr23:
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pushl $0 # err_code
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pushl $23 # int_no
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jmp interrupt_handler_prepare
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.global isr24
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.type isr24, @function
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isr24:
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pushl $0 # err_code
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pushl $24 # int_no
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jmp interrupt_handler_prepare
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.global isr25
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.type isr25, @function
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isr25:
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pushl $0 # err_code
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pushl $25 # int_no
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jmp interrupt_handler_prepare
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.global isr26
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.type isr26, @function
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isr26:
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pushl $0 # err_code
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pushl $26 # int_no
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jmp interrupt_handler_prepare
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.global isr27
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.type isr27, @function
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isr27:
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pushl $0 # err_code
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pushl $27 # int_no
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jmp interrupt_handler_prepare
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.global isr28
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.type isr28, @function
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isr28:
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pushl $0 # err_code
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pushl $28 # int_no
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jmp interrupt_handler_prepare
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.global isr29
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.type isr29, @function
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isr29:
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pushl $0 # err_code
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pushl $29 # int_no
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jmp interrupt_handler_prepare
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.global isr30
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.type isr30, @function
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isr30:
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# pushl $0 # err_code pushed by CPU
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pushl $30 # int_no
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jmp interrupt_handler_prepare
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.global isr31
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.type isr31, @function
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isr31:
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pushl $0 # err_code
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pushl $31 # int_no
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jmp interrupt_handler_prepare
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.global isr128
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.type isr128, @function
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isr128:
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pushl $0 # err_code
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pushl $128 # int_no
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jmp interrupt_handler_prepare
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.global isr130
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.type isr130, @function
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isr130:
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pushl $0 # err_code
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pushl $130 # int_no
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jmp interrupt_handler_prepare
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.global isr131
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.type isr131, @function
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isr131:
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pushl $0 # err_code
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pushl $131 # int_no
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jmp interrupt_handler_prepare
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.global irq0
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.type irq0, @function
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irq0:
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pushl $0 # err_code
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pushl $32 # int_no
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jmp interrupt_handler_prepare
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.global irq1
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.type irq1, @function
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irq1:
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pushl $0 # err_code
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pushl $33 # int_no
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jmp interrupt_handler_prepare
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.global irq2
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.type irq2, @function
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irq2:
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pushl $0 # err_code
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pushl $34 # int_no
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jmp interrupt_handler_prepare
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.global irq3
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.type irq3, @function
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irq3:
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pushl $0 # err_code
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pushl $35 # int_no
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jmp interrupt_handler_prepare
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.global irq4
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.type irq4, @function
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irq4:
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pushl $0 # err_code
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pushl $36 # int_no
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jmp interrupt_handler_prepare
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.global irq5
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.type irq5, @function
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irq5:
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pushl $0 # err_code
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pushl $37 # int_no
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jmp interrupt_handler_prepare
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.global irq6
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.type irq6, @function
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irq6:
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pushl $0 # err_code
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pushl $38 # int_no
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jmp interrupt_handler_prepare
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.global irq7
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.type irq7, @function
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irq7:
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pushl $0 # err_code
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pushl $39 # int_no
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jmp interrupt_handler_prepare
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.global irq8
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.type irq8, @function
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irq8:
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pushl $0 # err_code
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pushl $40 # int_no
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jmp interrupt_handler_prepare
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.global irq9
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.type irq9, @function
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irq9:
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pushl $0 # err_code
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pushl $41 # int_no
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jmp interrupt_handler_prepare
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.global irq10
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.type irq10, @function
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irq10:
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pushl $0 # err_code
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pushl $42 # int_no
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jmp interrupt_handler_prepare
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.global irq11
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.type irq11, @function
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irq11:
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pushl $0 # err_code
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pushl $43 # int_no
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jmp interrupt_handler_prepare
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.global irq12
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.type irq12, @function
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irq12:
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pushl $0 # err_code
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pushl $44 # int_no
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jmp interrupt_handler_prepare
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.global irq13
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.type irq13, @function
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irq13:
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pushl $0 # err_code
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pushl $45 # int_no
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jmp interrupt_handler_prepare
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.global irq14
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.type irq14, @function
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irq14:
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pushl $0 # err_code
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pushl $46 # int_no
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jmp interrupt_handler_prepare
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.global irq15
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.type irq15, @function
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irq15:
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pushl $0 # err_code
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pushl $47 # int_no
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jmp interrupt_handler_prepare
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.global yield_cpu_handler
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.type yield_cpu_handler, @function
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yield_cpu_handler:
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pushl $0 # err_code
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pushl $129 # int_no
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jmp interrupt_handler_prepare
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.global thread_exit_handler
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.type thread_exit_handler, @function
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thread_exit_handler:
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pushl $0 # err_code
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pushl $132 # int_no
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jmp interrupt_handler_prepare
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interrupt_handler_prepare:
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movl $1, asm_is_cpu_interrupted
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# Check if an interrupt happened while having kernel permissions.
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testw $0x3, 12(%esp) # cs
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jz fixup_relocate_stack
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fixup_relocate_stack_complete:
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pushl %eax
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pushl %ecx
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pushl %edx
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pushl %ebx
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pushl %esp
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pushl %ebp
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pushl %esi
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pushl %edi
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# Push the user-space data segment.
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movl %ds, %ebp
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pushl %ebp
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# Load the kernel data segment.
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movw $0x10, %bp
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movl %ebp, %ds
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movl %ebp, %es
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# Push CR2 in case of page faults
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movl %cr2, %ebp
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pushl %ebp
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# Push the current kernel errno value.
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movl global_errno, %ebp
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pushl %ebp
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# Push whether a signal is pending.
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movl asm_signal_is_pending, %ebp
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pushl %ebp
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# Now call the interrupt handler.
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movl %esp, %ebx
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subl $4, %esp
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andl $0xFFFFFFF0, %esp
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.global fake_interrupt
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.type fake_interrupt, @function
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fake_interrupt:
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movl %ebx, (%esp)
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call interrupt_handler
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movl %ebx, %esp
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load_interrupted_registers:
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# Restore whether signals are pending.
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popl %ebp
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movl %ebp, asm_signal_is_pending
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# Restore the previous kernel errno.
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popl %ebp
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movl %ebp, global_errno
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# Remove CR2 from the stack.
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addl $4, %esp
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# Restore the user-space data segment.
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popl %ebp
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movl %ebp, %ds
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movl %ebp, %es
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popl %edi
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popl %esi
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popl %ebp
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addl $4, %esp # Don't pop %esp, may not be defined.
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popl %ebx
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popl %edx
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popl %ecx
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popl %eax
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# Remove int_no and err_code
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addl $8, %esp
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movl $0, asm_is_cpu_interrupted
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# If interrupted with kernel permissions we may need to switch stack.
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testw $0x3, 4(%esp) # int_no and err_code now gone, so cs is at 4(%esp).
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jz fixup_switch_stack
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fixup_switch_stack_complete:
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# Return to where we came from.
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iret
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fixup_relocate_stack:
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# Ok, so some genius at Intel decided that if the permission level does not
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# change during an interrupt then the CPU won't push the stack pointer and
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# it won't reload it during iret. This seriously messes up the scheduler
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# that wants to preempt kernel threads each with their own stack. The
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# scheduler will attempt to read (and modify) the stack value which doesn't
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# exist and worse: the value at that location is likely used by the
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# interrupted kernel thread. A quick and dirty solution is to simply move
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# the stack 8 bytes down the stack. Right now there are the 5 elements on
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# the stack (eflags, cs, eip, err_code, int_no) of 5 bytes each.
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mov %eax, -4-8(%esp) # Save eax
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mov 0(%esp), %eax # int_no
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mov %eax, 0-8(%esp)
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mov 4(%esp), %eax # err_code
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mov %eax, 4-8(%esp)
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mov 8(%esp), %eax # eip
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mov %eax, 8-8(%esp)
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mov 12(%esp), %eax # cs
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mov %eax, 12-8(%esp)
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mov 16(%esp), %eax # eflags
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mov %eax, 16-8(%esp)
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# Next up we have to fake what the CPU should have done: pushed ss and esp.
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mov %esp, %eax
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addl $5*4, %eax # Calculate original esp
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mov %eax, 20-8(%esp)
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mov %ss, %eax
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mov %eax, 24-8(%esp)
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# Now that we moved the stack, it's time to really handle the interrupt.
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mov -4-8(%esp), %eax
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subl $8, %esp
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jmp fixup_relocate_stack_complete
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fixup_switch_stack:
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# Yup, we also have to do special processing when we return from the
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# interrupt. The problem is that if the iret instruction won't load a new
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# stack if interrupted with kernel permissions and that the scheduler may
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# wish to change the current stack during a context switch. We will then
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# switch the stack before calling iret; but iret needs the return
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# information on the stack (and now it isn't), so we'll copy our stack onto
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# our new stack and then fire the interrupt and everyone is happy.
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# In the following code, %esp will point our fixed iret return parameters
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# that has stack data. However, the processor does not expect this
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# information as cs hasn't changed. %ebx will point to the new stack plus
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# room for three 32-bit values (eip, cs, eflags) that will be given to the
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# actual iret. We will then load the new stack and copy the eip, cs and
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# eflags to the new stack. However, we have to be careful in the case that
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# we are switching to the same stack (in which case stuff on the same
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# horizontal location in the diagram is actually on the same memory
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# location). We therefore copy to the new stack and carefully avoid
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# corrupting the destination if %esp + 8 = %ebx, This diagram show the
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# structure of the stacks and where temporaries will be stored:
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# -12 -8 -4 %esp 4 8 12 16 20
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# old: IECX IEBX IEAX EIP CS EFLAGS ESP SS ...
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# new: IECX IEBX IEAX - - EIP CS EFLAGS ...
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# -20 -16 -12 -8 -4 %ebx 4 8 12
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mov %eax, -4(%esp) # IEAX, Clobbered as copying temporary
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mov %ebx, -8(%esp) # IEBX, Clobbered as pointer to new stack
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mov %ecx, -12(%esp) # IECX, Clobbered as new stack selector
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mov 12(%esp), %ebx # Pointer to new stack
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sub $3*4, %ebx # Point to eip on the new stack (see diagram)
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movw 16(%esp), %cx # New ss
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# The order of these does not matter if we are switching to the same stack,
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# as the memory would be copied to the same location (see diagram).
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mov -4(%esp), %eax # interrupted eax value
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mov %eax, -12(%ebx)
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mov -8(%esp), %eax # interrupted ebx value
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mov %eax, -16(%ebx)
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mov -12(%esp), %eax # interrupted ecx value
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mov %eax, -20(%ebx)
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# The order of these three copies matter if switching to the same stack.
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mov 8(%esp), %eax # eflags
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mov %eax, 8(%ebx)
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mov 4(%esp), %eax # cs
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mov %eax, 4(%ebx)
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mov 0(%esp), %eax # eip
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mov %eax, 0(%ebx)
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mov %cx, %ss # Load new stack selector
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mov %ebx, %esp # Load new stack pointer
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|
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mov -12(%esp), %eax # restore interrupted eax value
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|
mov -16(%esp), %ebx # restore interrupted ebx value
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|
mov -20(%esp), %ecx # restore interrupted ecx value
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|
|
|
jmp fixup_switch_stack_complete
|
|
.size interrupt_handler_prepare, . - interrupt_handler_prepare
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|
|
|
.global interrupt_handler_null
|
|
.type interrupt_handler_null, @function
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|
interrupt_handler_null:
|
|
iret
|
|
.size interrupt_handler_null, . - interrupt_handler_null
|
|
|
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.global load_registers
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|
.type load_registers, @function
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|
load_registers:
|
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# Let the register struct become our temporary stack
|
|
movl 4(%esp), %esp
|
|
jmp load_interrupted_registers
|
|
.size load_registers, . - load_registers
|