I hereby relicense all my work on Sortix under the ISC license as below. All Sortix contributions by other people are already under this license, are not substantial enough to be copyrightable, or have been removed. All imported code from other projects is compatible with this license. All GPL licensed code from other projects had previously been removed. Copyright 2011-2016 Jonas 'Sortie' Termansen and contributors. Permission to use, copy, modify, and distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
276 lines
6.5 KiB
C++
276 lines
6.5 KiB
C++
/*
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* Copyright (c) 2013, 2014, 2015, 2016 Jonas 'Sortie' Termansen.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* disk/ahci/hba.cpp
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* Driver for the Advanced Host Controller Interface.
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*/
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#include <errno.h>
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#include <stdarg.h>
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#include <sortix/kernel/addralloc.h>
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#include <sortix/kernel/descriptor.h>
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#include <sortix/kernel/interlock.h>
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#include <sortix/kernel/interrupt.h>
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#include <sortix/kernel/ioctx.h>
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#include <sortix/kernel/log.h>
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#include <sortix/kernel/panic.h>
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#include <sortix/kernel/pci.h>
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#include <sortix/kernel/pci-mmio.h>
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#include "../node.h"
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#include "ahci.h"
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#include "hba.h"
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#include "port.h"
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#include "registers.h"
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namespace Sortix {
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namespace AHCI {
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static inline void ahci_hba_flush(volatile struct hba_regs* hba_regs)
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{
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(void) hba_regs->ghc;
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}
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static unsigned long AllocateDiskNumber()
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{
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static unsigned long next_disk_number = 0;
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return InterlockedIncrement(&next_disk_number).o;
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}
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HBA::HBA(uint32_t devaddr)
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{
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this->devaddr = devaddr;
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memset(&mmio_alloc, 0, sizeof(mmio_alloc));
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memset(&ports, 0, sizeof(ports));
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interrupt_registered = false;
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mmio_alloced = false;
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}
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HBA::~HBA()
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{
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// TODO: Destroy all the ports?
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if ( interrupt_registered )
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Interrupt::UnregisterHandler(interrupt_index, &interrupt_registration);
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if ( mmio_alloced )
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UnmapPCIBar(&mmio_alloc);
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}
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void HBA::LogF(const char* format, ...)
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{
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// TODO: Print this line in an atomic manner.
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Log::PrintF("ahci: pci 0x%X: ", devaddr);
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va_list ap;
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va_start(ap, format);
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Log::PrintFV(format, ap);
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va_end(ap);
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Log::PrintF("\n");
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}
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bool HBA::Reset()
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{
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#if 0 // We probably don't want to do this?
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// Indicate that system software is AHCI aware.
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regs->ghc = regs->ghc | GHC_AE;
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regs->ghc = regs->ghc | GHC_HR;
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ahci_hba_flush(regs);
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while ( (regs->ghc & GHC_HR) )
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kthread_yield();
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regs->ghc = regs->ghc | GHC_AE;
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ahci_hba_flush(regs);
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// TODO: Set port enable bits in Port Control and Status on Intel
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// controllers.
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#endif
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return true;
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}
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void HBA::OnInterrupt()
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{
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uint32_t is = regs->is;
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if ( !is )
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return;
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for ( size_t i = 0; i < sizeof(ports) / sizeof(ports[0]); i++ )
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{
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if ( !(is & (1U << i)) )
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continue;
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if ( ports[i] )
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ports[i]->OnInterrupt();
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}
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regs->is = is;
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}
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void HBA__OnInterrupt(struct interrupt_context*, void* context)
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{
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((HBA*) context)->OnInterrupt();
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}
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bool HBA::Initialize(Ref<Descriptor> dev, const char* devpath)
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{
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pcibar_t mmio_bar = PCI::GetBAR(devaddr, 5);
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if ( mmio_bar.size() < sizeof(struct hba_regs) && /* or || ? */
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mmio_bar.size() < 1024 )
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{
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LogF("error: register area is too small");
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return errno = EINVAL, false;
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}
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if ( !MapPCIBAR(&mmio_alloc, mmio_bar, 0) )
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{
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LogF("error: registers could not be mapped: %m");
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return false;
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}
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regs = (volatile struct hba_regs*) mmio_alloc.from;
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if ( 4 < sizeof(void*) && !(regs->cap & CAP_S64A) )
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{
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LogF("error: controller doesn't support 64-bit addressing");
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return errno = EINVAL, false;
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}
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// TODO: Take control from BIOS?
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#if 0
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// TODO: Is it bad to do a hard reset?
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if ( !Reset() )
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{
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LogF("error: could not reset");
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return false;
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}
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#else
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regs->ghc = regs->ghc | GHC_AE;
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#endif
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regs->ghc = regs->ghc & ~GHC_IE;
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uint32_t ports_implemented = regs->pi;
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uint32_t num_ports = CAP_NCS(regs->cap);
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uint32_t actual_ports = 0;
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for ( uint32_t i = 0; i < num_ports; i++ )
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{
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if ( !(ports_implemented & (1 << i)) )
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continue;
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actual_ports++;
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if ( regs->ports[i].pxcmd & (PXCMD_ST | PXCMD_CR |
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PXCMD_FRE | PXCMD_FR) )
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{
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if ( regs->ports[i].pxcmd & (PXCMD_ST | PXCMD_CR) )
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{
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regs->ports[i].pxcmd = regs->ports[i].pxcmd & ~PXCMD_ST;
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if ( !WaitClear(®s->ports[i].pxcmd, PXCMD_CR, true, 500) )
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{
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LogF("error: port %u: "
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"timeout waiting for PXCMD_CR to clear", i);
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ports_implemented &= ~(1 << i);
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continue;
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}
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}
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if ( regs->ports[i].pxcmd & (PXCMD_FRE | PXCMD_FR) )
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{
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regs->ports[i].pxcmd = regs->ports[i].pxcmd & ~PXCMD_FRE;
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if ( !WaitClear(®s->ports[i].pxcmd, PXCMD_FR, true, 500) )
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{
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LogF("error: port %u: "
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"timeout waiting for PXCMD_FR to clear", i);
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ports_implemented &= ~(1 << i);
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continue;
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}
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}
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}
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regs->ports[i].pxis = regs->ports[i].pxis;
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regs->ports[i].pxserr = regs->ports[i].pxserr;
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}
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regs->is = regs->is;
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for ( uint32_t i = 0; i < num_ports; i++ )
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{
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if ( !(ports_implemented & (1 << i)) )
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continue;
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if ( !(ports[i] = new Port(this, i)) )
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{
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LogF("error: failed to allocate port %u", i);
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continue;
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}
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if ( !ports[i]->Initialize() )
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{
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delete ports[i];
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ports[i] = NULL;
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continue;
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}
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}
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interrupt_index =
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Interrupt::IRQ0 + PCI::Read8(devaddr, PCIFIELD_INTERRUPT_LINE);
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interrupt_registration.handler = HBA__OnInterrupt;
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interrupt_registration.context = this;
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Interrupt::RegisterHandler(interrupt_index, &interrupt_registration);
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interrupt_registered = true;
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// Enable interrupts.
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regs->ghc = regs->ghc | GHC_IE;
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ahci_hba_flush(regs);
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for ( uint32_t i = 0; i < num_ports; i++ )
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{
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if ( ports[i] && !ports[i]->FinishInitialize() )
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{
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//ports[i]->Destroy();
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// TODO: WARNING: FIXME: Shut down the port here, see the function
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// ahci_port_destroy in the OS `kiwi'!
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// TODO: Unsafe with respect to interrupt handler.
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delete ports[i];
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ports[i] = NULL;
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continue;
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}
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}
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for ( uint32_t i = 0; i < num_ports; i++ )
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{
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if ( !ports[i] )
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continue;
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unsigned long number = AllocateDiskNumber();
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char name[4 + sizeof(unsigned long) * 3];
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snprintf(name, sizeof(name), "ahci%lu", number);
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Ref<PortNode> node(new PortNode(ports[i], 0, 0, 0660, dev->dev, 0));
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if ( !node )
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PanicF("Unable to allocate memory for %s/%s inode", devpath, name);
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ioctx_t ctx; SetupKernelIOCtx(&ctx);
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if ( LinkInodeInDir(&ctx, dev, name, node) != 0 )
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PanicF("Unable to link %s/%s to AHCI driver inode", devpath, name);
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}
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return true;
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}
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} // namespace AHCI
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} // namespace Sortix
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